Two kinds of projects can be created under Slix™ Tool:

• SOCBlox Project: The purpose of an SOCBlox project is to create an EDIF netlist output that can be dropped in a seperate FPGA project. A single or multiple IP cores can be selected in an SOCBlox project.
• IPMix Project: An IPMix project is a complete FPGA design that generates the FPGA programming bitstream file. Slix™ Tool software automatically adds the necessary HDL modules to implement the desired functionality based on the IP cores selection.

Slix™ Tool compliant IP cores contain user friendly Slix™ Tags metadata, which are embedded within the IP core top-level RTL file. Any generic IP core can also be imported into the Slix™ Tool library by using the GUI based Generic IP core import process. For more information about Slix™ Tool IP core compliance requirements, please refer to the Slix™ Tags Reference Guide.

The Knowledgebase file provides all the intelligence needed by Slix™ Tool in order to automatically connect the various IP cores and support modules. The Knowledgebase file can be easily viewed or edited using visual mind map software. Slix™ Tool provides option to import/export the knowledgebase file between the visual mind map and XML formats.

Slix™ Tool essentially hides all the FPGA design complexities due to its patent pending innovative technology, which provides:

• GUI based customization of individual IP cores in the design
• Targetting the design on multiple FPGA vendor devices
• Automatic generation of top level RTL file and addition of appropriate support modules
• Automatic generation of constraint files and batch files to execute the FPGA vendor specific back-end command line tools
• Automatic, Project specific, HTML document generation